MEMS includes integrated micro devices, such as mechanical, optical and thermal sensing components, formed on a substrate made of a single or composite layers of solid state materials. The MEMS is preferably fabricated by using the state-of-art wafer batch processing techniques to form those micro devices, sized from nanometers to millimeters, on a solid state substrate like a silicon wafer. Those MEMS devices are operating for sensing, controlling, and actuating various mechanical, optical or chemical functions on a micro scale, individually in single units or collaboratively in arrays for generating coordinated overall effects on a macro scale. Typical applications of such MEMS devices include, but not limited to, accelerometers, gyroscopes, pressure sensors, chemical and flow sensors, micro-optics devices, optical scanners, fluid flow control devices, chemical sensing and chemical delivery systems, and biological sensors among many others.
Furthermore, MEMS devices are preferably fabricated together in a unified process with supporting integrated circuit (IC) devices on the same semiconductor substrate as an integrated silicon device, namely as an integrated MEMS. Advantageously, such integrated MEMS in a single chip solution not only greatly reduce the size, weight and power consumption but also enhance the performance of an application system when compared with the conventional construction which separates MEMS and supporting IC as different micro devices.
Fabrication of MEMS devices employs many of the same processing steps as the fabrication of IC. In particular, the formation of an MEMS device involves depositing and patterning thin films on a substrate, such as a silicon wafer, to produce complex micro devices. Solid state thin film materials commonly used include but not limited to silicon dioxide, silicon nitride, polycrystalline silicon (poly), amorphous silicon, aluminum, copper, refractory metals and their oxide or nitride compounds.
However, to achieve certain mechanical, optical or thermal functions of MEMS devices, it is necessary to spatially decouple selected micro structural elements in MEMS devices to form a gap or cavity between the decoupled and the rest. Such decoupling of micro structural elements in MEMS devices enables certain desired mechanical, thermal, chemical or optical functions as required. For example, a number of MEMS motion sensors contain two or more micro structural elements which are spatially separated but could move relatively to each other.
In many MEMS devices, cavities and suspended structural elements under encapsulation, in vacuum or filled with selective gases, are necessities to be fabricated only through a wafer-level micro machining process. One of the most widely used approaches to form a gap or cavity and thus to suspend the structural elements in an MEMS device involves selective etching a solid sacrificial layer or element. This sacrificial layer is first formed before the structural element and then as the underline physical supporting base, enables deposition and patterning of the structural element. After depositing the sacrificial layer and forming the structural element, photolithographic masking, patterning and etching steps are employed to remove the sacrificial layer, completely or at least partially.
Eventually, no matter at which later stages during the whole fabrication process of such MEMS devices, the sacrificial layer is selectively removed, either completely or at least partially, to release the structural element. And finally, the structural element needs to be enclosed in a cavity or encapsulated, either in vacuum or filled with selective gases, in a typical MEMS packaging process.
Scheme of fabricating the structural element formation while removing the sacrificial layer as well as encapsulating the structural element are core to the thin film based MEMS fabrication. It is extremely desirable that such schemes are substantially compatible to typical CMOS wafer fabrication processes, using the available thin film materials and their deposition and patterning process methods on standard CMOS thin film equipment and process line. This is where the prior art to date fails to address successfully.